Synopsys, Inc. announced that NextIO, a provider of I/O virtualization, has standardized on the VMM methodology, as defined in the Verification Methodology Manual for SystemVerilog, and on Synopsys' VCS functional verification product to accelerate the SystemVerilog-based verification of their newest I/O virtualization chip design. NextIO was able to create its own unique base classes derived from the VMM base classes that they are now able to extend on a project-by-project basis.

    Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs. This complete verification environment enabled NextIO to achieve first-pass functional silicon success. The need for more flexibility, functionality and performance across multiple levels of design is driving demand for better tools and technology. Whether designing high performance electro-mechanical flight systems or a multi-processor SoC, designers are facing formidable challenges to deliver high quality product designs on time. Verification of these state-of-the-art systems is becoming a severe bottleneck as designers face the sometimes daunting task of eliminating all the bugs in their design.

    According to Rich Warwick, vice president of Engineering and Operations at NextIO, "After an extensive evaluation of the solutions in the market, we decided to use VMM to address the challenge of creating a modern, powerful SystemVerilog-based verification environment. The VMM methodology and Synopsys' implementation of the VMM base classes helped us structure a verification environment that utilized the full power of SystemVerilog. By standardizing all of our testbenches on VMM, we have been able to reduce development time by fifty percent. VMM solved every verification challenge we faced."

    This standardization significantly reduces the learning curve for NextIO's designers and verification engineers when new chips are developed, shortening the development schedules of future designs. Subsequent designs will require a certain amount of new, design-specific code; however, NextIO expects to reuse eighty to ninety percent of the environment they architected for their second-generation chip. This flexible approach allows NextIO to quickly assemble both unit-level and chip-level testbenches in a standardized fashion.

    "The adoption of the VMM methodology by innovative companies such as NextIO reflects a growing, industry-wide trend. The combination of Synopsys' comprehensive VCS functional verification product and customer-proven VMM base class library enables unprecedented productivity and predictability, making the VMM methodology the solution of choice for SystemVerilog-based design and verification," commented Swami Venkat, senior director of Verification Marketing at Synopsys.