Xilinx, Inc. announced that its DSP development tools now deliver up to a 38 percent faster Fmax performance for multi-rate DSP designs and improved ease of use. Using System Generator for DSP, developers of multi-rate DSP designs, typical of wireless and defense applications, will see up to a 38 percent improvement in Fmax performance when using version 9.2 with no modification to existing designs.

    With the release of version 9.2 of the AccelDSP synthesis tool and System Generator for DSP, the development tool component of the Xilinx XtremeDSP solution, provides higher-levels of performance as well as a tighter integration between the two tools to simplify the FPGA design flow for developers who use both the MATLAB and Simulink modeling environments concurrently. The System Generator for DSP tool and AccelDSP synthesis tool are each sold separately and available immediately through the Xilinx Online Store . The System Generator for DSP tool and AccelDSP synthesis tool are priced at $995 and $4995 respectively.  

    A new mapping algorithm has been implemented that uses register duplication and placement based on recursive partitioning of loads on high fanout nets typical of multi-rate designs. This and other enhancements deliver the ease of use, levels of abstraction, and quality of results demanded by designers new to FPGAs who are increasingly selecting programmable logic as their hardware platform of choice.

    "Until two years ago, our surveys showed that maximum MIPS were always the top criteria in a development team's choice of chip to use in a DSP application," said Will Strauss, president of Forward Concepts. "But with today's increasing chip complexity and time-to-market pressures, development tools are now the key item for chip selection, and Xilinx is taking a leadership role in addressing designer needs."

    Unlike disjointed design flows which require separate algorithm development and RTL coding steps, System Generator for DSP provides an integrated modeling and verification environment that enables a smooth path from initial design capture in Simulink to FPGA design closure, without the need to learn or use traditional RTL design methodologies. The AccelDSP synthesis tool is a high-level MATLAB language based tool for designing DSP blocks for Xilinx FPGAs that automates floating- to fixed-point conversion, generates synthesizable VHDL or Verilog, and creates a test bench for verification. Designers can generate a fixed-point C++ model or System Generator block from a MATLAB algorithm.

    "DSP optimized FPGAs such as the low-cost Spartan-3A DSP family and Virtex-5 platform FPGAs are quickly being adopted into new and emerging markets by design teams without traditional FPGA design expertise," said Tom Feist, marketing director for Xilinx Embedded and Signal Processing Solutions. "The System Generator for DSP and AccelDSP tools enable these design teams to quickly assess the performance, cost and power benefits of an FPGA-based implementation for their unique applications and to develop final implementations that fully leverage the unique FPGA device resources using tools and languages familiar to algorithm and system level designers."